1. Field of the Invention
The invention generally relates to a device for generating a pair of true/complement-phase (T/C-phase) logic signals. More particularly, the present invention relates to a device for generating a pair of true/complement-phase (T/C-phase) logic signals with feedback control.
2. Description of Related Art
In recent years, since the processing speed of computer has been significantly enhanced, the data transmission interface and data processing method have to be developed to meet the requirement of the computer. Traditionally, when using the transistor-transistor logic (TTL) signal level for parallel transmission of data, cables with number of wires same as the number of bits of the bandwidth of the data signal are required. Hence, when all the voltage levels of the bits of the data signal are changed at the same time, a significant noise is generated. The noise may reduce the rate of data transmission drastically. In addition, the length of the cables is limited due to the decay of the data signals during the signal transmission. Therefore, the differential signal pairs for transmission data signal in series has been developed for achieving higher transmission rate and lower noise level.
In general, the serial data transmission process is performed by transmitting the bits of the data at the same clock period in series. Hence, the differential signal transmission process is performed by using a voltage pairs with 180° phase difference to transmit a signal, wherein the voltage difference between the voltage pairs represents the value of the signal being transmitted. The advantage of differential signal transmission is that the noise generated by the conventional TTL input signal is effectively reduced. Specially, since the signal is transmitted by using two wires to send the pair of the voltages, the two noises of each voltage transmitted by the two wires are similar at the same time. Therefore, the two noises are generally called as the common mode transmission noise, and almost all the noises of the signal will be eliminated by the subtraction of the voltage pairs. Hence, when the signal is detected by measuring the difference between the voltage pairs, the common mode transmission noise will be eliminated. Therefore, in the serial differential signal transmission, only a pair of low-level voltages with 180° phase difference is required. However, in the traditional TTL signal transmission, a high-level voltage signal is required to prevent the signal from attenuation.
FIG. 1 is a waveform diagram schematically illustrating an excellent differential signal. Generally, the low-level differential signal include a pair of signals D+ and D−. The voltage levels of the pair of signals V(D+) and V(D−) can be obtained from the common mode voltage VCM±the differential voltage VDIFF. In addition, for example, a logic signal 1 is defined as V(D+)−V(D−)>0, and a logic signal 0 is defined as V(D+)−V(D−)<0.
FIG. 2 is a diagram schematically illustrating a conventional single-end true/complete (T/C)-phase logic signal converter. This signal converter 200 includes inverters 202, 204, and 206, and a differential amplifier 208. The signal converter 200 receives a single-end logic signal S. Thereafter, the single-end logic signal S is converted by the inverters 202 and 204 to generate a logic signal O+, and converted by the inverter 206 to generate a logic signal O−. Hence, the phase difference between the two logic signals O+ and O− is 180°, and thus a T/C-phase logic signal pair is constructed by the two logic signals O+ and O−. Then, the two logic signals O+ and O− are entered into the input terminals of the differential amplifier 208. Then, the differential amplifier 208 will output the low-level differential signals D+ and D− directly corresponding to the logic signals O+ and O−. However, since the signal O+ is generated via two inverters and the signal O− is only generated via one inverter, the waveform of the differential signals D+ and D− are not symmetrical in time axis. As shown in FIG. 3, the rising time TR and the falling time TF of the signal O+ fall behind the falling time TF and the rising time TR of the signal O−, thus the logic signals 1 and 0 that generated by subtracting the signals O+ and O− will alter. Therefore, the reliability of signal receiving and decoding is reduced. Further, the intersection of the signals D+ and the signals D− is defined as the common mode voltage VCM. As shown in FIG. 3, if the differential signals D+ and D− are not symmetrical, the common mode voltage VCM cannot be fixed at a certain voltage level. In general, the intersections of signals D+ and D− are easily affected by the length of the wire and the load connected the amplifier. In addition, since the conventional T/C-phase logic signal converter does not have a feedback loop, the converter is easily affected by the variation of process and the operation condition. Therefore, a device and a method for generating a precise T/C-phase logic signal pair is necessary.